1. Field
This disclosure generally relates to electronic design automation. More specifically, this disclosure relates to methods and apparatuses for routing nets over circuit blocks in a hierarchical circuit design.
2. Related Art
Rapid advances in computing technology have made it possible to perform trillions of computational operations each second on data sets that are sometimes as large as trillions of bytes. These advances can largely be attributed to the dramatic improvements in electronic design automation technologies which have made it possible to integrate tens of millions of devices onto a single chip.
Routing is one such electronic design automation technology in which nets are routed to electrically link circuit elements while satisfying the design rules. Typically, a router is given a set of pins or terminals, where each pin is associated with a net. The router's task is to route wires so that all pins associated with the same net are electrically linked together, and pins that are associated with different nets are not electrically linked together. The router typically needs to route the nets so that certain design rules are met. Further, the router can optionally be given a set of pre-determined routes.
The top-level hierarchy in a circuit design can contain a large number of nets which electrically link the terminals of the top-level circuit blocks. These nets can be routed in channels between the blocks and/or over the top of the blocks. Slew and/or timing problems can occur in nets that are routed over a large block, and hence, it is generally desirable to reduce or prevent the occurrence of slew and/or timing problems in such situations.
FIG. 1 illustrates a net that is routed over a circuit block in a hierarchical circuit design.
Circuit design 100 can include circuit blocks 102, 104, and 106. Terminal 108 in circuit block 102 may be desired to be electrically linked with terminal 110 in circuit block 106. A routing engine may route net 112 over circuit block 104 to electrically link terminals 108 and 110. If the portion of net 112 that is routed over circuit block 104 is too long, it may not meet slew and/or timing requirements. Adding buffers or repeaters before and/or after net 112 crosses circuit block 104 may not be sufficient to solve the slew and/or timing problems.
Unfortunately, conventional routing approaches that attempt to fix or avoid such routing-related problems have serious drawbacks. One approach is to prohibit all routing over large blocks. Unfortunately, this approach is impractical because today's chips have active areas that cover 80-90% of the total chip area, and prohibiting all routing over large blocks will most probably make the chip unroutable.
A second approach is to increase the size of the driver that is driving the net. Unfortunately, increasing the size of the driver can create other problems, such as electron-migration problems. Hence, this approach is also not desirable.
A third approach is to create “feedthrough” nets that go through a block (instead of being routed over the block) so that the nets can be buffered inside the block. This approach may work for a few nets, but the approach is impractical for general use because of the sheer number of nets that need to be routed. Furthermore, it is very difficult to allocate and use resources efficiently in this approach.
A fourth approach is to selectively expose some buffers (also known as embedded repeaters) inside a block so that their pins are visible at the top level and can be used to buffer long nets that are being routed over the block. This approach is also impractical because it interrupts the circuit block's floorplan and routing. Moreover, it is very difficult to allocate and use resources efficiently in this approach.
Hence, what is needed is a technique for routing nets in a hierarchical circuit design without the above-described drawbacks.